In the simulation of the waveform, we not only want to see the waveform of the port signal designed in the Top layer, but also want to observe how the internal signal changes, so we find the internal signal in the Sim window and put it in the wave for observation.
MODELSIM 10 COMMAN CODE
What should we do?Ģ: do test_tb.fdo #Re-execute the script for simulation after modifying the code Perhaps the result of the simulation is not what we want, we must modify the code and then simulate. Then you can observe the simulated waveform file. Note: Each line in test_tb.fdo can be executed line by line in the ModelSim Transcript window. #Enter the simulation settings, the time unit is 1ps, the library is designated as work, and AES256_tb refers to the name of your top layer designġ4: do #<-Execute script fileĢ: # ** Warning: (vlib-34) Library already exists at "work".ģ: # Model Technology ModelSim SE vcom 6.5 Compiler 2009.01 Jan 22Ģ009 #<-The message obtained by compiling test.vhdħ: # - Loading package std_logic_unsignedĩ: # - Compiling architecture test of testġ0: # Model Technology ModelSim SE vcom 6.5 Compiler 2009.01 Jan 22ġ4: # - Loading package std_logic_unsignedġ6: # - Compiling architecture behavior of test_tbġ7: # vsim -lib work -t 1ps test_tb #simulation setting command lineĢ1: # Loading ieee.std_logic_unsigned(body)Ģ2: # Loading work.test_tb(behavior)#1 #Loading test_tbĢ3: #. Start simulation, -c option makes vsim work in commandline mode -l option is to output log file to vsim.log -do option is to run tcl script file after starting simulation -L option Is the designated work logic library work.foo is the simulated top level module.ġ: vlib work #Create a library named work, which must be done before this simulationĢ: vcom -explicit -93 "SBOX_ROM.vhd" #Compile vhd codeħ: vcom -explicit -93 "round_key_BRAM.vhd"ĩ: vcom -explicit -93 "Keyexpansion_Yao.vhd"ġ0: vcom -explicit -93 "AES256_ENC_DEC.vhd" vmap-Map the logical library name to the specified directory View the error details: verror ** (error number code)Įstablish a logic library work in the current directory, and the work folder will be found in the current directory after running. Exit the simulation, enter the command: quit –sim //Very commonly used!!ħ. Start the simulation, enter the command, run 3us, then the simulation waveform appears in the waveform windowĦ. To add a signal to the waveform window, enter the command: add wave -hex *, where * means to add all signals in the design, -hex means to represent the wave in hexadecimalĥ. Open the waveform window and enter the command: view waveĤ. Add a drive to the clock signal, enter the command: force clk 0 0,1 10 -r 20, set the simulation clock to 50MHz (set the time unit as ns)ģ. Run the simulation, enter the command in the main window: vsim work. P.S.: Modelsim 10.0a seems to not support this feature although it is not mentioned in the technote.1. What is the solution to get generic packages with protected type working with Modelsim? Using generic packages works fine without a protected type and protected types in a normal package also. I also tried to put the package instantiation in a separate file but the results stays the same. # ** INTERNAL ERROR: pkgref: export lookup failed for package #0 When executing this do file Modelsim compiles both files and while loading the libraries for the simulation it fails with. Vcom -work work -2008 -novopt test_generic_pkg.vhd tb.vhd This two files can be tested with the sim.do file: vlib work
Variable cnt : unsigned(15 downto 0) := to_unsigned(0, 16) Īssert false report to_string(test.get) severity note Impure function get return std_logic_vector isĪn used by an entity/architecture tb.vhd: package test_pkg is new work.test_generic_pkg generic map( WIDTH => 16 ) Procedure set(d : std_logic_vector(WIDTH-1 downto 0)) is
Variable data : std_logic_vector(WIDTH-1 downto 0) Impure function get return std_logic_vector Procedure set(d : std_logic_vector(WIDTH-1 downto 0))
Now I have a generic package test_generic_pkg.vhd: library ieee You can write your own generic package, instantiate it,Īnd use it. It is reasonable to use this to instantiate the generic fixed and float Generics cannot depend on other generics in the same generic list.the generic package can be instantiated as a design unit, but not in.generic lists on package can contain constant generics and package.The technote vhdl2008.note states:Ī basic generic package and its instantiation with some noteworthy I am trying to use generic packages with a protected type in Modelsim 10.0a.
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